A microprocessor is generally incorporated in devices that perform image processing requiring high performance. The examples of such devices are laser beam printers or image recognizing apparatuses. Instruction codes and data such as constants or initial values required for the image processing are stored in a main memory provided outside of the microprocessor. This microprocessor also includes therein a cache memory. The microprocessor performs the processing by using basically the instruction codes and the data stored in the main memory or the cache memory.
In order to distinguish data in the narrow sense signifying numerical data such as constants or initial values (including characters) from data in the broad sense including instruction codes in addition of the data in the narrow sense, in this specification the data in the broad sense is simply referred to as “data” while the data in the narrow sense is referred to as “numerical data.”
In general, the cache memory constitutes a logical memory hierarchy with the main memory. The main memory is constituted of a typical DRAM (a dynamic RAM) or the like. The cache memory is constituted of an SRAM (a static RAM) or the like which can be faster accessed as compared to the main memory.
The accessed instruction code or numerical data is stored in the cache memory together with instruction codes or numerical data therearound. If an access is made to the instruction code or numerical data stored in the cache memory, the instruction code or numerical data is read from not the main memory but the cache memory. Consequently, since the frequency of accesses to the slow main memory is reduced, the processing speed increases.
A physical address in the main memory and a physical address in the cache memory are assigned to the instruction code or numerical data stored in the cache memory. Naturally, both the physical addresses are different from each other. If the instruction code or numerical data to be accessed is not present in the cache memory when the memory is accessed, then the physical address of the main memory is designated. By contrast, if the instruction code or numerical data to be accessed is present in the cache memory, the physical address of the cache memory is designated.
Such address conversion is automatically performed by address conversion means called a tag register and a cache control unit incorporated in a processor. Therefore, a programmer need not pay any attention to the presence of the cache memory. Similarly, the microprocessor incorporates therein memory management units (MMUs) so as to control the access in the main memory.
These address conversion means set one physical address within a certain logical address range. Simultaneously with this, the address conversion means define common access attributes and the like within the set range. A load module includes the instruction code or the numerical data for use in executing the instruction code which has a different type of access. However, the address conversion means in a part of a cache control unit and the memory management unit handles the instruction code and the numerical data in the same manner without any distinction.
However, in a memory access mechanism by the use of the above-described cache memory, if the data to be processed becomes vast, for example, as in the case of image processing, the cache memory is frequently rewritten. Consequently, the local instruction code or numerical data, for which the cache memory in itself should function effectively, may be swapped out of the cache memory. Therefore, the hit rate of the cache memory is decreased, so that the effect of high-speed processing cannot be sufficiently produced. Further, if the capacity of the main memory is increased so as to incorporate large amount of data then its access speed decreases.
Use of high-speed and large-capacity cache memory can prevent the cache memory from being frequently rewritten even in the case where the large scale data is processed. However, such a high-speed and large-capacity memory is expensive. In contrast, use of an inexpensive memory of a large capacity may sacrifice an access time.